1. Field of the Invention
The present invention relates to a method for resetting a plasma display panel, and more particularly, to a method for resetting a plasma display panel initially performed in a unit sub-field which is a minimum drive period for a 3-electrode surface discharge type plasma display panel so that wall charges in all display cells are uniformly distributed and made suitable for addressing to be performed in the next step.
2. Description of the Related Art
FIG. 1 shows a typical 3-electrode surface discharge type plasma display panel. FIG. 2 shows an example of a display cell of the panel of FIG. 1. Referring to FIGS. 1 and 2, in a typical surface discharge plasma display panel 1, address electrode lines A1, A2, . . . , Am−1, and Am, front and rear dielectric layers 11 and 15, Y electrode lines Y1, . . . , Yn, X electrode lines X1, . . . , Xn, fluorescent substance 16, a plurality of partition walls 17, and a protective layer 12 which is a magnesium monoxide (MgO) layer, are provided between front and rear glass substrates 10 and 13.
The address electrode lines A1, A2, . . . , Am−1, and Am are formed in a predetermined pattern on the front surface of the rear glass substrate 13. The rear dielectric layer 15 is coated on the front surface of the rear glass substrate 13 where the address electrode lines A1, A2, . . . , Am−1, and Am are formed. The partition walls 17 are formed on the front surface of the rear dielectric layer 15 parallel to the address electrode lines A1, A2, . . . , Am−1, and Am. The partition walls 17 section a discharge area of each display cell and prevent cross talk between the neighboring display cells. The fluorescent substance 16 is coated on the surfaces between the partition walls 17.
The X electrode lines X1, . . . , Xn and Y electrode lines Y1, . . . , Yn are formed on the rear surface of the front glass substrate 10 perpendicular to the address electrode lines A1, A2, . . . , Am−1, and Am. Each cross point sets a corresponding display cell. Each of the X electrode lines X1, . . . , Xn is formed of a transparent electrode line Xna of FIG. 2, which is formed of a transparent conductive material such as ITO (indium tin oxide), and a metal electrode line Xnb of FIG. 2 to increase conductivity. Each of the Y electrode lines Y1, . . . , Yn is formed of transparent electrode line Yna of FIG. 2, which is formed of a transparent conductive material such as ITO (indium tin oxide), and a metal electrode line Ynb of FIG. 2 to increase conductivity. The front dielectric layer 11 is coated on the rear surface of the front glass substrate 10 where the X electrode lines X1, . . . , Xn and Y electrode lines Y1, . . . , Yn are formed. A protective layer 12, for example, a MgO layer, for protecting the panel 1 from a strong electric field is coated on the rear surface of the front dielectric layer 11. A plasma generating gas is sealed in the discharge space 14.
FIG. 3 shows a typical driving apparatus of the plasma display panel 1 of FIG. 1. Referring to FIG. 3, the typical driving apparatus of the plasma display panel 1 includes an image processor 66, a logic controller 62, an address driver 63, an X driver 64, and a Y driver 65.
The image processor 66 converts an external analog image signal into a digital signal and generates an internal image signal, for example, an 8-bit red (R) image data, an 8-bit green (G) image data, an 8-bit blue (B) image data, a clock signal, and vertical and horizontal sync signals. The logic controller 62 generates drive control signals SA, SY, and SX according to the internal image signal output from the image processor 66. The address driver 63 processes the address signal SA of the drive control signals SA, SY, and SX output from the logic controller 62 to generates a display data signal. The generated display data signal is applied to the address electrode lines A1, A2, . . . , Am−1, and Am. The X driver 64 processes the X drive control signal SX of the drive control signals SA, SY, and SX output from the logic controller 62 to apply the processed signal to the X electrode lines X1, . . . , Xn. The Y driver 65 processes the Y drive control signal SY of the drive control signals SA, SY, and SX output from the logic controller 62 to apply the processed signal to the Y electrode lines Y1, . . . , Yn.
FIG. 4 shows a typical address-display separation driving method with respect to the Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 4, a unit frame is divided into 8 sub-fields SF1, . . . , SF8 to realize a time-sharing gray-scale display. Also, each of the sub-field SF1, . . . , SF8 is divided into address periods A1, . . . , A8 and maintenance discharge periods S1, . . . , S8.
In each of the address periods A1, . . . , A8, scanning pulses corresponding to each of the Y electrode lines Y1, . . . , Yn of FIG. 1 are sequentially applied simultaneously when the display data signal is applied to the address electrode lines A1, A2, . . . , Am−1, and Am of FIG. 1. Accordingly, if a high-level display data signal is applied while the scanning pulses are applied, it generates address discharges and form wall charges in selected discharge cells.
In each of the maintenance discharge periods S1, . . . , S8, maintenance discharge pulses are alternately applied to all of the Y electrode lines Y1, . . . , Yn and all of the X electrode lines X1, . . . , Xn. Then, display discharge is generated in the discharge cells where wall charges are formed during the address periods A1, . . . , A8. Thus, the brightness of the plasma display panel is proportional to the length of the maintenance discharge periods S1, . . . , S8 in the unit frame. The length of the maintenance discharge periods S1, . . . , S8 in the unit frame is 255 T, in which T is a unit time. As a result, 256 grade-scales including a case of never being displayed in the unit frame can be displayed.
Here, a time 1T corresponding to 20 is set for the maintenance discharge period S1 of the first sub-field SF1. A time 2T corresponding to 21 is set for the maintenance discharge period S2 of the second sub-field SF2. A time 4T corresponding to 22 is set for the maintenance discharge period S3 of the third sub-field SF3. A time 8T corresponding to 23 is set for the maintenance discharge period S4 of the fourth sub-field SF4. A time 16T corresponding to 24 is set for the maintenance discharge period S5 of the fifth sub-field SF5. A time 32T corresponding to 25 is set for the maintenance discharge period S6 of the sixth sub-field SF6. A time 64T corresponding to 26 is set for the maintenance discharge period S7 of the seventh sub-field SF7. A time 128T corresponding to 27 is set for the maintenance discharge period S8 of the eighth sub-field SF8.
Accordingly, by appropriately selecting a sub-field of the eight sub-fields to be displayed, a total of 256 gradations including a case of not being displayed in any of the sub-fields can be displayed.
In the above plasma display panel driving method, in each of the address periods A1, . . . , A8, resetting is performed so that wall charges of all display cells are uniformly distributed and are made suitable for addressing to be performed in the next step.
FIG. 5 shows waveforms of signals applied to electrode lines of a plasma display panel according to a conventional resetting method. FIG. 6 shows the distribution of wall charges in a display cell at the time of t3 of FIG. 5. FIG. 7 shows the distribution of wall charges in a display cell at the time of t4 of FIG. 5. FIG. 8 shows the level of illumination SL of light generated from a plasma display panel corresponding to driving signals of FIG. 5.
The conventional resetting method as shown in FIG. 5 is disclosed in Japanese Patent Publication Nos. 2000-214,823 and 2000-242,224. In FIG. 5, reference numeral SRY denotes a driving signal applied to all of the Y electrode lines Y1, . . . , Yn of FIG. 1, reference numeral SRX denotes a driving signal applied to all of the X electrode lines X1, . . . , Xn of FIG. 1, and reference numeral SRA denotes a driving signal applied to all of the address electrode lines A1, . . . , Am of FIG. 1.
Referring to FIGS. 5 through 8, in the first reset step (t1–t2), a voltage applied to the X electrode lines X1, . . . , Xn are gradually increased up to a first voltage VBX, for example, 190 V, from a ground voltage VG as a fourth voltage. Here, the ground voltage VG is applied to the Y electrode lines Y1, . . . , Yn and the address electrode lines A1, . . . , Am. Accordingly, weak discharges occur between the X electrode lines X1, . . . , Xn and the Y electrode lines Y1, . . . , Yn, and the X electrode lines X1, . . . , Xn and the address electrode lines A1, . . . , Am. Then, wall charges having the second polarity, that is, the negative polarity, are formed around the X electrode lines X1, . . . , Xn.
In the second reset step (t2–t3), a voltage applied to the Y electrode lines Y1, . . . , Yn is gradually increased up to a second voltage VBYP, for example, 400 V from a fifth voltage VBYM, for example, 180 V. The second voltage VBYP is much higher than the first voltage VBX and the fifth voltage VBYM is slightly lower than the first voltage VBX. Here, the ground voltage VG is applied to the X electrode lines X1, . . . , Xn and the address electrode lines A1, . . . , Am. Accordingly, a weak discharge is generated between the Y electrode lines Y1, . . . , Yn and the X electrode lines X1, . . . , Xn while a weaker discharge is generated between the Y electrode lines Y1, Yn and the address electrode lines A1, . . . , Am. Here, the discharge between the Y electrode lines and the X electrode lines is stronger than that between the Y electrode lines and the address electrode lines because numerous wall charges having the negative polarity are formed around the X electrode lines as the first reset step (t1–t2) is performed. Thus, numerous wall charges having the negative polarity are formed around the Y electrode lines Y1, . . . , Yn. Wall charges having the first polarity, that is, the positive polarity, are formed around the X electrode lines X1, . . . , Xn. Wall charges having the positive polarity are formed less around the address electrode lines A1, . . . , Am (Please refer to FIG. 6).
In the third reset step (t3–t4), while the voltage applied to the X electrode lines X1, . . . , Xn is maintained at the first voltage VBX, the voltage applied to the Y electrode lines Y1, . . . , Yn is gradually lowered down to the ground voltage VG. Here, the ground voltage VG is applied to the address electrode lines A1, . . . , Am. Accordingly, a weak discharge is generated between the X electrode lines X1, . . . , Xn and the Y electrode lines Y1, . . . , Yn so that some of the wall charges having the negative polarity around the Y electrode lines Y1, . . . , Yn move toward the X electrode lines X1, . . . , Xn (Please refer to FIG. 7). Here, since the ground voltage VG is applied to the address electrode lines A1, . . . , Am, the number of the wall charges having the positive polarity around the address electrode lines A1, . . . , Am slightly increases.
Accordingly, in the subsequent addressing step, a display data signal having the positive polarity is applied to the selected address electrode lines A1, . . . , Am and a scanning signal having the negative polarity is sequentially applied to the Y electrode lines Y1, . . . , Yn, so that a smooth addressing can be performed.
However, according to the conventional resetting method, even through wall charges having the negative polarity are formed around the X electrode lines X1, . . . , Xn in the first reset step t1–t2, the same ground voltage VG is applied to the X electrode lines X1, . . . , Xn and the address electrode lines A1, . . . , Am in the second reset step (t2–t3). Therefore, the following problems occur.
First, an unnecessary strong discharge is generated between the Y electrode lines Y1, . . . , Yn and the X electrode lines X1, . . . , Xn in the second reset step (t2–t3). This lowers the contrast of the plasma display panel. Also, unnecessarily numerous wall charges of the positive polarity formed around the X electrode lines generate an excessively strong discharge between the Y electrode lines and the X electrode lines in the third reset step (t3–t4). This further lowers the contrast of a plasma display panel, as illustrated in FIG. 8.
Second, relatively weak discharge between the Y electrode lines and the address electrode lines in the second reset step (t2–t3) forms insufficient wall charges of the positive polarity around the address electrode lines (Please refer to FIG. 6). Accordingly, wall charges of the positive polarity finally formed around the address electrode lines A1, . . . , Am are insufficient as shown in FIG. 7, and they are not sufficient for the selected display cells in the subsequent addressing.